1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which includes memory cells. More particularly, it relates to a semiconductor integrated circuit capable of enhancing a bus occupation rate of data irrespective of the frequency of a clock signal. It also relates to a method of controlling the semiconductor integrated circuit for enhancing a bus occupation rate of data irrespective of the frequency of a clock signal.
The present invention also relates to a variable delay circuit capable of setting a delay time at a predetermined value.
2. Description of the Related Art
The operating speeds of semiconductor integrated circuits have steadily been heightened owing to the progress of semiconductor manufacturing technology. In particular, the operating frequency of a logic LSI such as microcomputer has yearly been improving and the difference thereof from the operating frequency of a memory LSI such as DRAM has been increasing.
In order to reduce such differences, there have been developed high-speed DRAMs such as EDO DRAM (Extended Data Output DRAM), SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate Synchronous DRAM), and Direct RDRAM (Rambus DRAM).
The high-speed DRAMs of this type are possible to read and write data from and into memory cells at high speed by successively accessing the memory cells connected to an identical word line. Concretely, there has been developed a DRAM whose maximum operating frequency exceeds 100 MHz. The high-speed DRAMs are often employed for the main storages of personal computers and workstations.
Meanwhile, the high-speed DRAMs of this type are used for not only personal computers and workstations but also the components of application products of microcomputers. In this case, the operating frequencies of the high-speed DRAMs are determined in accordance with the specifications of each product. Therefore, the operating frequency of the high-speed DRAM for such uses is set at, for example, 50 MHz or 75 MHz even in the case of setting the maximum operating frequency at 133 MHz.
When the high-speed DRAM is operated at the frequency lower than the maximum operating frequency, there arise some problems to be explained below.
FIG. 1(a) shows a read timing when the cycle xe2x80x9ctCKxe2x80x9d of a clock signal CLK is 20 ns (50 MHz).
By way of example, an SDRAM performs a read operation by receiving a read command RD which activates a circuit relevant to column addresses after the reception of an activation command ACTV which activates a circuit relevant to row addresses. In the following description, commands shall be expressed as xe2x80x9cACTV commandxe2x80x9d, xe2x80x9cRD commandxe2x80x9d, or the like.
In this SDRAM, the minimum time of a xe2x80x9ctRCDxe2x80x9d (/RAS to /CAS Delay time) is set at 18 ns. The tRCD is a time from the reception of the ACTV command to that of a command corresponding to a column address such as the RD command.
In addition, the minimum time of a xe2x80x9ctCACxe2x80x9d (/CAS Access time from Clock) is set at 14 ns. The tCAC is a time from the reception of the command corresponding to the command address to the outputting of read data.
The tRCD, the tCAC, and a xe2x80x9ctACxe2x80x9d indicated in FIG. 1(b) are specifications necessary for properly operating the SDRAM and each value of them does not depend upon the operating frequency of the SDRAM in the identical products. In the following description, the clock signal CLK shall be called xe2x80x9cCLK signalxe2x80x9d.
In the case of operating the SDRAM at 50 MHz, the minimum time of the tRCD (18 ns) is less than the cycle of the CLK signal (20 ns). Therefore, the SDRAM can receive the RD command at the rising edge of the CLK signal (at 20 ns) as is next to that of the CLK signal corresponding to the reception of the ACTV command. The tRCD becomes 20 ns actually. In addition, the minimum time of the tCAC (14 ns) is less than the cycle of the CLK signal (20 ns). Therefore, the SDRAM outputs the read data QA0 the tCAC (14 ns) after the rising edge of the CLK signal as corresponds to the reception of the RD command. As a result, an access time tRAC (/RAS Access time from Clock) from the reception of the ACTV command to the outputting of the read data QA0 becomes 34 ns (tCK+tCAC).
On the other hand, FIG. 1(b) shows a read timing in the case where the cycle xe2x80x9ctCKxe2x80x9d of a CLK signal is 13 ns (about 75 MHz).
Here, the maximum time of the xe2x80x9ctACxe2x80x9d (Access time from Clock) is set at 6 ns. The tAC is a time from the rising edge of the clock signal to the outputting of read data.
In the case of operating the SDRAM at 75 MHz, the minimum time of a xe2x80x9ctRCDxe2x80x9d (18 ns) is greater than the cycle of the CLK signal (13 ns). Therefore, the SDRAM receives an RD command at the second rising edge of the CLK signal (at 26 ns) after the reception of an ACTV command. The tRCD becomes 26 ns actually. In addition, the minimum time of a xe2x80x9ctCACxe2x80x9d (14 ns) is greater than the cycle of the CLK signal (13 ns). Therefore, the SDRAM outputs the read data QA0 the tAC (6 ns) after the rising edge of the CLK signal next to that of the CLK signal corresponding to the reception of the RD command. As a result, an access time tRAC becomes 45 ns (3xc2x7tCK+tAC).
In the above read operations, the CLK signal at the higher frequency has the longer access time tRAC. In other words, the CLK signal at the higher frequency has the lower bus occupation rate of data, which causes a problem. Here, the xe2x80x9cbus occupation ratexe2x80x9d is a rate at which valid data are transmitted onto a data bus during a predetermined period. Therefore, the low bus occupation rate leads to degrading the performance of the whole system.
FIG. 2(a) shows a precharge operation which proceeds after an ACTV command in the case where the cycle xe2x80x9ctCRxe2x80x9d of a clock signal CLK is 20 ns (50 MHz). The precharge operation is an operation of charging a bit line to a predetermined voltage so as to inactivate a circuit relevant to row addresses.
In this SDRAM, the minimum time of a xe2x80x9ctRASxe2x80x9d (/RAS active time) is set at 24 ns. The tRAS is a time from the reception of an ACTV command to that of a precharge command PRE.
In addition, the minimum time of a xe2x80x9ctRPxe2x80x9d (/RAS Precharge time) is set at 10 ns. The tRP is a time from the reception of the PRE command to that of the next ACTV command. The tRAS, the tRP, and a xe2x80x9ctDPLxe2x80x9d indicated at FIG. 2(b) are specifications necessary for properly operating the SDRAM and each value of them does not depend upon the operating frequency of the SDRAM in the identical products.
When operating the SDRAM at 50 MHz, the minimum time of the tRAS (24 ns) becomes greater than the cycle of the CLK signal (20 ns). Therefore, the SDRAM receives the PRE command at the second rising edge of the CLK signal (at 40 ns) after the reception of the ACTV command. The actual tRAS would be 40 ns. In addition, the SDRAM performs the precharge operation during the period of the tRP (10 ns) after the reception of the PRE command. Therefore, a cycle time xe2x80x9ctRCxe2x80x9d (/RAS Cycle time) from the reception of the ACTV command to that of the next ACTV command becomes 60 ns (3xc2x7tCK).
On the other hand, FIG. 2(b) shows a write operation accompanying a precharge operation in the case where the cycle xe2x80x9ctCKxe2x80x9d of a clock signal CLK is 20 ns (50 MHz).
Here, a WRA command (WRite with Auto-precharge) is a command for causing the SDRAM to automatically perform the precharge operation after the write operation. The minimum time of a xe2x80x9ctRCDxe2x80x9d is set at 18 ns the same as in the ordinary read command RD (FIG. 1) or write command WR (not shown). The minimum time of a xe2x80x9ctDPLxe2x80x9d (Data-in to Precharge Lead time) is set at 10 ns. The tDPL is a time from the reception of write data to that of a precharge command PRE.
In operating the SDRAM at 50 MHz, the minimum time of the tRCD (18 ns) is less than the cycle of the CLK signal (20 ns) as in FIG. 1(a). Therefore, the SDRAM can receive the WRA command at the rising edge of the CLK signal (at 20 ns) next to that of the CLK signal corresponding to the reception of an ACTV command.
The SDRAM simultaneously accepts the write data (not shown) with the WRA command and writes the accepted data into a memory cell during the period of the tDPL. Thereafter, the SDRAM performs the precharge operation during the period of a xe2x80x9ctRPxe2x80x9d. The total of the tDPL and tRP is 20 ns, which is equal to one cycle tCK of the CLK signal. Therefore, the SDRAM can receive the next ACTV command at the rising edge of the CLK signal (at 40 ns) as is next to that of the CLK signal corresponding to the reception of the WRA command. Accordingly, a cycle time xe2x80x9ctRCxe2x80x9d (/RAS Cycle time) from the reception of the ACTV command to that of the next ACTV command becomes 40 ns (2xc2x7tCK).
In this manner, the cycle time tRC becomes shorter in performing the precharge operation together with the write operation than in performing the precharge operation alone. This causes a problem that the operation speed heightens in the more complicated operation.
FIG. 3 shows a different timing of the precharge operation of the SDRAM.
FIG. 3(a) shows the precharge operation after an ACTV command in the case where the cycle xe2x80x9ctCKxe2x80x9d of a clock signal CLK is 13 ns (75 MHz).
In operating the SDRAM at 75 MHz, the minimum time of a xe2x80x9ctRASxe2x80x9d (24 ns) becomes greater than the cycle of the CLK signal (13 ns). Therefore, the SDRAM receives a PRE command at the second rising edge of the CLK signal (at 26 ns) after the reception of the ACTV command. The actual tRAS would be 26 ns. In addition, the SDRAM performs the precharge operation during the period of a xe2x80x9ctRPxe2x80x9d (10 ns) after the reception of the PRE command. Therefore, a cycle time xe2x80x9ctRCxe2x80x9d (/RAS Cycle time) from the reception of the ACTV command to that of the next ACTV command becomes 39 ns (3xc2x7tCK).
On the other hand, (b) FIG. 3 shows a write operation accompanying the precharge operation in the case where the cycle xe2x80x9ctCKxe2x80x9d of a clock signal CLK is 13 ns (75 MHz).
In operating the SDRAM at 75 MHz, the minimum time of a xe2x80x9ctRCDxe2x80x9d (18 ns) is greater than the cycle of the CLK signal (13 ns). Therefore, the SDRAM receives a WRA command at the second rising edge of the CLK signal (at 26 ns) after the reception of an ACTV command. Besides, the SDRAM accepts write data (not shown) simultaneously with the WRA command and writes the accepted data into a memory cell during the period of a xe2x80x9ctDPLxe2x80x9d. Thereafter, the SDRAM performs the precharge operation during the period of a xe2x80x9ctRPxe2x80x9d. The total of the tDPL and tRP is 20 ns, which is greater than one cycle tCK of the CLK signal. Therefore, the SDRAM can receive the next ACTV command at the second rising edge of the CLK signal (at 52 ns) after the reception of the WRA command. Accordingly, a cycle time xe2x80x9ctRCxe2x80x9d (/RAS Cycle time) from the reception of the ACTV command to that of the next ACTV command becomes 52 ns (4xc2x7tCK).
At the timing shown in FIG. 2(b) or FIG. 3(b), the CLK signal at the higher frequency delays the write operation, which causes a problem. Moreover, the CLK signal at the higher frequency lowers the bus occupation rate in the write operation.
Besides, at the operation timings (FIG. 3) at the higher frequency, the cycle time tRC during which the precharge operation is performed together with the write operation, becomes longer than the cycle time tRC during which the precharge operation is performed alone. This relation is opposite to that at the operating timings (FIG. 2) at the lower frequency. In other words, the cycle time tRC necessary for the respective operations do not depend upon the level of the frequency. This poses a problem that a timing design is difficult when operating the high-speed DRAM of this type mounted in the application products of the microcomputer, at the frequency lower than the maximum operating frequency thereof.
An object of the present invention is to provide a semiconductor integrated circuit capable of increasing the bus occupation rate of data independent of the operating frequency thereof and a method of controlling the semiconductor integrated circuit for increasing the bus occupation rate of data independent of the operating frequency thereof.
Another object of the present invention is to provide a variable delay circuit capable of setting a delay time to a predetermined length.
According to one of the aspects of a semiconductor integrated circuit in the present invention, a plurality of memory cells connected to a word line, a row control circuit, a column control circuit, a command control circuit, and a timing adjusting circuit are comprised. The row control circuit is first operated and the word line is activated when a read or a write operation is performed in the memory cell in the semiconductor integrated circuit. Subsequently, the command control circuit receives a column operation command in synchronization with a clock signal and operates the column control circuit. The timing adjusting circuit has the function of setting a delay time, which is from the reception of the column operation command to the start of the operation of the column control circuit, to be variable. Under the control of the timing adjusting circuit, the column control circuit initiates the operation a predetermined length of the delay time after the reception of the column operation command. Then, a read operation or a write operation in the memory cell selected by the word line being activated is performed.
Delaying the operation of the column control circuit in this manner results in performing a read or a write operation in the memory cell at the optimum timing corresponding to that of an internal circuit independent of the cycle of the clock signal. This increases the number of times in receiving commands per unit time and the bus occupation rate of read data or write data. Moreover, a read cycle time and a write cycle time can be shortened since the column control circuit is operated at the optimum timing corresponding to that of the internal circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets a delay time to a predetermined length in accordance with a latency. The latency is the number of clock cycles from the reception of the column operation command to the performance of a read or a write operation and it is set in accordance with the frequency of the clock signal supplied. Therefore, the column control circuit can perform a read operation and a write operation at the optimum timings in accordance with the frequency of the clock signal.
The timing adjusting circuit is constructed of simple delay circuits or the like since the delay time is set variable in accordance with the latency.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit is readily able to set a delay time to a predetermined length, for example, by switching over a no plurality of delay circuits.
According to another aspect of the semiconductor integrated circuit in the present invention, the start of the operation of the column control circuit is delayed in synchronization with the delayed clock signal so that the operations of the column control circuit and other internal circuits can be precisely controlled.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length in accordance with the actual operating timing of the row control circuit, the timing shifting due to the changes of a supply voltage, a temperature, or the like. Therefore, the column control circuit can be operated at the optimum timing corresponding to that of the row control circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length for every operation of the row control circuit. Since the frequency of setting the delay times is increased, the column control circuit can be precisely operated.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length when the row control circuit has operated in the inactive state of the internal circuit. This results in decreasing the frequency of setting the delay time and reducing the power consumption.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length in response to the reception of a refresh command for refreshing the memory cells. This results in decreasing the frequency of setting the delay time and reducing the power consumption.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length in response to the reception of the first refresh command after the power is switched on. This results in decreasing the frequency of setting the delay time and reducing the power consumption.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length in response to a request to adjust the delay time from the exterior. Therefore, the delay time is set variable in accordance with changes in the external environment such as a supply voltage. As a result, the delay time can be set only if necessary.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a mode register for setting an operating mode from the exterior. The timing adjusting circuit sets the delay time to a predetermined length in accordance with a value set by the mode register. By using the mode register, the delay time can be set only if necessary.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length in accordance with a control signal fed to a control terminal. This enables the immediate setting of the delay time when a supply voltage, for example, has fluctuated.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a plurality of memory cells connected to a bit line, a precharging circuit, a command control circuit, and a timing adjusting circuit. When the semiconductor integrated circuit performs a precharge operation for setting the bit line to have a predetermined voltage, the command control circuit first receives a precharge command in synchronization with a clock signal and then operates the precharging circuit. The timing adjusting circuit has the function of setting a delay time, which is from the reception of the precharge command to the start of the operation of the precharging circuit, to be variable. Under the control of the timing adjusting circuit, the precharging circuit initiates the operation a predetermined length of the delay time after the reception of the precharge command. Then, the precharge operation is performed.
Delaying the operation of the precharging circuit in this manner makes it possible to perform the precharge operation at the optimum timing corresponding to that of an internal circuit independent of the cycle of the clock signal. As a result, the number of times in receiving commands per unit time is increased. It is accordingly possible to enhance the bus occupation rate of read data or write data. Moreover, shortening a precharge cycle time is possible since the precharging circuit is operated at the optimum timing corresponding to that of the internal circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length in accordance with a latency. Since the latency is set in accordance with the frequency of the clock signal supplied, the precharging circuit can perform the precharge operation at the optimum timing in accordance with the frequency of the clock signal.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit can readily set the delay time to a predetermined length, for example, by switching over a plurality of delay circuits.
According to another aspect of the semiconductor integrated circuit in the present invention, the start of the precharge operation is delayed in synchronization with the delayed clock signal so that the precharge operation can be precisely controlled.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing adjusting circuit sets the delay time to a predetermined length in accordance with the actual operating timing of the row control circuit, the timing shifting in accordance with a supply voltage, a temperature, or the like. This results in operating the precharging circuit at the optimum timing corresponding to that of the row control circuit.
According to one of the aspects of a method of controlling a semiconductor integrated circuit in the present invention, when a read or a write operation is performed in the memory cell, a row control circuit is first operated and a word line is activated. Subsequently, a column control circuit operates upon the reception of a column operation command in synchronization with a clock signal. Here, a delay time from the reception of the column operation command to the start of the operation of the column control circuit is set variable. Therefore, the column control circuit initiates the operation a predetermined length of delay time after the reception of the column operation command. The read or the write operation in the memory cell selected by the word line being activated is performed.
Delaying the operation of the column control circuit in this manner makes it possible to perform a read or a write operation in the memory cell at the optimum timing corresponding to that of an internal circuit independent of the cycle of the clock signal. This results in increasing the number of times in receiving commands per unit time and the bus occupation rate of read data or write data. Moreover, it is possible to perform a read operation and a write operation at high speed since the column control circuit is operated at the optimum timing corresponding to that of the internal circuit.
According to another aspect of the method of controlling the semiconductor integrated circuit in the present invention, when a precharge operation for setting a bit line to have a predetermined voltage is performed, a precharging circuit operates upon receiving a precharge command in synchronization with a clock signal. Here, a delay time from the reception of the precharge command to the start of the operation of the precharging circuit is set variable so that the precharge circuit initiates the operation a predetermined length of delay time after the reception of the precharge command. Then, the precharge operation is performed.
Delaying the operation of the precharge circuit in this manner makes it possible to perform the precharge operation at the optimum timing corresponding to that of an internal circuit independent of the cycle of the clock signal. This results in increasing the number of times in receiving commands per unit time. It is accordingly possible to enhance the bus occupation rate of read data or write data.
According to one of the aspects of a variable delay circuit in the present invention, the first delay circuit, the second delay circuit, a detecting circuit and a selecting circuit are comprised. The first delay circuit is constructed by connecting a plurality of the first delay stages in cascade and it receives an input signal at the initial one of the first delay stages. The second delay circuit is constructed by connecting in cascade the second delay stages identical to the first delay stages and it receives the first timing signal at the initial one of the second delay stages. The detecting circuit receives the second timing signal and detects, of delayed timing signals outputted from each of the second delay stages, the one having a transition edge near the transition edge of the second timing signal. The selecting circuit selects a delayed signal outputted from the first delay stage corresponding to the second delay stage outputting the delayed timing signal detected by the detecting circuit.
As a result, the input signal can be delayed by a time from the transition edge of the first timing signal to that of the second timing signal. Besides, it is possible to adjust the delay time of the input signal by operating the detecting circuit if necessary. That is, the power consumption can be reduced by controlling the frequency of detecting the delay timing signal by the detecting circuit from the exterior.